CRYVISIL/docs/source/interlinks/network/Cryvisil-Net.rst
author Heinz Junkes <junkes@fhi-berlin.mpg.de>
Mon, 15 Jan 2018 11:21:30 +0100
changeset 6 55949e8c66c3
permissions -rw-r--r--
First commit

-------------------------------
Cryvisil connections (hardware)
-------------------------------

This is an overview of the connections (ethernet, serial)

.. uml::
   
   @startuml
   
   node Switch48Port
   node Switch12Port
   node MVME6100
   node Moxa01

   Switch48Port <-> Switch12Port

   Switch12Port <-> MVME6100
   Switch12Port <-> Moxa01 

   cloud Moxa01 {
       node moxa01
       node PfeifferTPG256A
       node CPUDebug
   }
 
   moxa01 <-[#CCCCCC]down-> PfeifferTPG256A : P2
   moxa01 <-[#CCCCCC]down-> CPUDebug : P1 to Debug, 9600 Baud
   @enduml